802 search results - page 16 / 161 » A comparative study of power efficient SRAM designs |
VIP
2000
13 years 9 months ago
2000
Transporting video over asynchronous transfer mode (ATM) networks has been an active area of research. The Variable Bit rate (VBR) service in ATM networks is primarily designed an...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract - This paper studies design considerations for lowpower ultra wideband (UWB) receiver architectures. First, three different architectures for the impulse-radio UWB transce...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
CF
2005
ACM
13 years 9 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...