802 search results - page 18 / 161 » A comparative study of power efficient SRAM designs |
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
VTC
2007
IEEE
14 years 1 months ago
2007
IEEE
— The characterization of downlink traffic power is an important issue for the design of efficient call admission control (CAC) and radio resource management (RRM) procedures. In...
ICC
2007
IEEE
14 years 2 months ago
2007
IEEE
: Increasing speed of hardware device and versatile functionalities of small equipments e.g. laptop, PDA etc. are introducing various voice oriented applications with mobility. Lik...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...