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ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
15 years 8 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
HPCA
2007
IEEE
16 years 4 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
152
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EUROPAR
2004
Springer
15 years 9 months ago
Large-Scale Deployment in P2P Experiments Using the JXTA Distributed Framework
The interesting properties of P2P systems (high availability despite peer volatility, support for heterogeneous architectures, high scalability, etc.) make them attractive for dist...
Gabriel Antoniu, Luc Bougé, Mathieu Jan, S&...
IPPS
2003
IEEE
15 years 9 months ago
Parallel Detection of Regulatory Elements with gMP
The detection of regulatory elements from a large set of regulatory regions is a challenging problem in computational genomics. However, computational methods to extract this biol...
Bertil Schmidt, Lin Feng, Amey V. Laud, Yusdi Sant...
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
15 years 9 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...