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ICFP
2012
ACM
11 years 10 months ago
Nested data-parallelism on the gpu
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
Lars Bergstrom, John H. Reppy
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
HPCA
2008
IEEE
14 years 8 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
HPCA
2006
IEEE
14 years 8 months ago
DMA-aware memory energy management
As increasingly larger memories are used to bridge the widening gap between processor and disk speeds, main memory energy consumption is becoming increasingly dominant. Even thoug...
Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricard...
CONEXT
2006
ACM
14 years 1 months ago
Migrating home agents towards internet-scale mobility deployments
While the IETF standardization process of the Mobile IPv6 and Network Mobility (NEMO) protocols is almost complete, their large-scale deployment is not yet possible. With these te...
Ryuji Wakikawa, Guillaume Valadon, Jun Murai