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» A decoupled KILO-instruction processor
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SIGMETRICS
2011
ACM
196views Hardware» more  SIGMETRICS 2011»
13 years 4 months ago
Performance analysis of the OP2 framework on many-core architectures
We present a performance analysis and benchmarking study P2 “active” library, which provides an abstraction framework for the solution of parallel unstructured mesh applicatio...
M. B. Giles, Gihan R. Mudalige, Z. Sharif, Graham ...
PPOPP
2012
ACM
12 years 5 months ago
DOJ: dynamically parallelizing object-oriented programs
We present Dynamic Out-of-Order Java (DOJ), a dynamic parallelization approach. In DOJ, a developer annotates code blocks as tasks to decouple these blocks from the parent executi...
Yong Hun Eom, Stephen Yang, James Christopher Jeni...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
IEEEPACT
2000
IEEE
14 years 2 months ago
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
Sang Jeong Lee, Pen-Chung Yew
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
14 years 3 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh