100 search results - page 17 / 20 » A decoupled KILO-instruction processor |
ISCA
1999
IEEE
14 years 2 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ISCA
2003
IEEE
14 years 3 months ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
Embedded single-chip heterogeneous multiprocessor (SCHM) systems experience frequent system events such as task preemption, power-saving voltage/frequency scaling, or arrival of n...
SIGMOD
2010
ACM
14 years 2 months ago
2010
ACM
We present SecureBlox, a declarative system that unifies a distributed query processor with a security policy framework. SecureBlox decouples security concerns from system speci...