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» A design platform for 90-nm leakage reduction techniques
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CASES
2008
ACM
13 years 9 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
14 years 2 months ago
Gate replacement techniques for simultaneous leakage and aging optimization
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao,...
CODES
2008
IEEE
14 years 2 months ago
System-level mitigation of WID leakage power variability using body-bias islands
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
Siddharth Garg, Diana Marculescu
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 8 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
14 years 2 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...