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» A design platform for 90-nm leakage reduction techniques
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CASES
2004
ACM
14 years 1 months ago
Reducing both dynamic and leakage energy consumption for hard real-time systems
While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for t...
Linwei Niu, Gang Quan
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
14 years 2 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
DAC
1999
ACM
13 years 12 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
ISLPED
2010
ACM
153views Hardware» more  ISLPED 2010»
13 years 7 months ago
Leakage minimization using self sensing and thermal management
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
Alireza Vahdatpour, Miodrag Potkonjak
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
13 years 5 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu