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GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
ISCAS
2007
IEEE
136views Hardware» more  ISCAS 2007»
14 years 1 months ago
Flexible Low Power Probability Density Estimation Unit For Speech Recognition
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
Ullas Pazhayaveetil, Dhruba Chandra, Paul Franzon
NOCS
2009
IEEE
14 years 2 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
ICC
2007
IEEE
102views Communications» more  ICC 2007»
14 years 2 months ago
A Scalable Wireless Channel Emulator for Broadband MIMO Systems
: This paper addresses the issue of designing scalable prototypes for multi input multi output (MIMO) wireless channel emulation. To date, emulators are extending single input sing...
Hamid Eslami, Ahmed M. Eltawil
DAC
2005
ACM
14 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo