182 search results - page 20 / 37 » A distributed processor state management architecture for la... |
OTM
2004
Springer
14 years 1 months ago
2004
Springer
Exceptionally large amounts of both distributed data and computational resources are becoming available through the Grid. This will enable efficient exchange and processing of very...
PDP
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
As increasingly larger memories are used to bridge the widening gap between processor and disk speeds, main memory energy consumption is becoming increasingly dominant. Even thoug...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...