Sciweavers

228 search results - page 46 / 46
» A dynamic scheduling approach to designing flexible safety-c...
Sort
View
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 28 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
DAC
1998
ACM
14 years 2 days ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
JSAC
2007
189views more  JSAC 2007»
13 years 7 months ago
Non-Cooperative Power Control for Wireless Ad Hoc Networks with Repeated Games
— One of the distinctive features in a wireless ad hoc network is lack of any central controller or single point of authority, in which each node/link then makes its own decision...
Chengnian Long, Qian Zhang, Bo Li, Huilong Yang, X...