195 search results - page 6 / 39 » A fast algorithm for power grid design |
126
Voted
GLVLSI
2010
IEEE
15 years 5 months ago
2010
IEEE
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
137
Voted
FSE
1997
Springer
15 years 7 months ago
1997
Springer
Most encryption algorithms are designed without regard to their performance on top-of-the-line microprocessors. This paper discusses general optimization principles algorithms desi...
112
Voted
ICCAD
2006
IEEE
16 years 11 days ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
127
Voted
DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
116
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ASPDAC
2009
ACM
15 years 8 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...