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» A functional formalization of on chip communications
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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 11 days ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
DAC
2006
ACM
14 years 7 months ago
Synthesis of synchronous elastic architectures
A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automat...
Jordi Cortadella, Michael Kishinevsky, Bill Grundm...
ACL
1998
13 years 8 months ago
Managing Information at Linguistic Interfaces
A large spoken dialogue translation system imposes both engineering and linguistic constraints on the way in which linguistic information is communicated between modules. We descr...
Johan Bos, C. J. Rupp, Bianka Buschbeck-Wolf, Mich...
EMSOFT
2010
Springer
13 years 4 months ago
PinaVM: a systemC front-end based on an executable intermediate representation
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
Kevin Marquet, Matthieu Moy
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
14 years 7 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...