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DSD
2007
IEEE
114views Hardware» more  DSD 2007»
14 years 2 months ago
General Digit-Serial Normal Basis Multiplier with Distributed Overlap
We present the architecture of digit-serial normal basis multiplier over GF(2m ). The multiplier was derived from the multiplier of Agnew et al. Proposed multiplier is scalable by...
Martin Novotný, Jan Schmidt
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
FPT
2005
IEEE
134views Hardware» more  FPT 2005»
14 years 1 months ago
Post-Silicon Debug Using Programmable Logic Cores
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
Bradley R. Quinton, Steven J. E. Wilton
EUROCAST
2001
Springer
189views Hardware» more  EUROCAST 2001»
14 years 16 days ago
Assertion-Based Analysis of Hybrid Systems with PVS
Abstract. Hybrid systems are a well-established mathematical model for embedded systems. Such systems, which combine discrete and continuous behavior, are increasingly used in safe...
Erika Ábrahám-Mumm, Ulrich Hannemann...
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
14 years 13 days ago
Meeting Delay Constraints in DSM by Minimal Repeater Insertion
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
I-Min Liu, Adnan Aziz, D. F. Wong