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RTAS
2010
IEEE
13 years 6 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
14 years 2 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong
NCA
2006
IEEE
13 years 7 months ago
Evolutionary training of hardware realizable multilayer perceptrons
The use of multilayer perceptrons (MLP) with threshold functions (binary step function activations) greatly reduces the complexity of the hardware implementation of neural networks...
Vassilis P. Plagianakos, George D. Magoulas, Micha...
ICST
2009
IEEE
13 years 5 months ago
Proving Functional Equivalence of Two AES Implementations Using Bounded Model Checking
Bounded model checking--as well as symbolic equivalence checking--are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC ha...
Hendrik Post, Carsten Sinz
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 2 months ago
Compact hardware design of Whirlpool hashing core
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
Timo Alho, Panu Hämäläinen, Marko H...