1013 search results - page 165 / 203 » A hardware implementation of realloc function |
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...