1013 search results - page 55 / 203 » A hardware implementation of realloc function |
CSREAESA
2006
13 years 9 months ago
2006
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
WSCG
2003
13 years 9 months ago
2003
We present a real-time rendering algorithm that generates soft shadows of dynamic scenes using a single light sample. As a depth-map algorithm it can handle arbitrary shadowed sur...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...