In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
Recently, there has been considerable interest in providing “trusted computing platforms” using hardware — TCPA and Palladium being the most publicly visible examples. In th...
David Lie, Chandramohan A. Thekkath, Mark Horowitz
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
For the last decade, Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry and the academic community and has been the subject of several standards. T...
Guerric Meurice de Dormale, Jean-Jacques Quisquate...
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...