1013 search results - page 73 / 203 » A hardware implementation of realloc function |
ICCAD
1996
IEEE
14 years 3 days ago
1996
IEEE
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
ICCAD
1994
IEEE
14 years 2 days ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
ETS
2007
IEEE
14 years 2 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...