2209 search results - page 324 / 442 » A high performance JPEG2000 architecture |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...