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DAC
2004
ACM
14 years 11 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
IPPS
2003
IEEE
14 years 3 months ago
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction
Percolation has recently been proposed as a key component of an advanced program execution model for future generation high-end machines featuring adaptive data/code transformatio...
Adeline Jacquet, Vincent Janot, Clement Leung, Gua...
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
12 years 15 days ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
DAC
1992
ACM
14 years 2 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
IWSOC
2005
IEEE
131views Hardware» more  IWSOC 2005»
14 years 3 months ago
Very High Radix Scalable Montgomery Multipliers
This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w × v – bit integer multipliers in place of...
Kyle Kelley, David Harris