159 search results - page 10 / 32 » A high throughput 3D-bus interconnect for network processors |
CSREAESA
2006
13 years 8 months ago
2006
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
DATE
1998
IEEE
13 years 11 months ago
1998
IEEE
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing archi...
CCGRID
2006
IEEE
14 years 1 months ago
2006
IEEE
— Widespread use of cluster systems in diverse set of applications has spurred significant interest in providing high performance cluster interconnects. A major inefficiency in...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...