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» A low complexity hardware architecture for motion estimation
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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 1 months ago
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
Sudeep Pasricha, Nikil D. Dutt
DAC
1999
ACM
13 years 12 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
ICCD
2000
IEEE
107views Hardware» more  ICCD 2000»
14 years 4 months ago
Architectural Impact of Secure Socket Layer on Internet Servers
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
Krishna Kant, Ravishankar K. Iyer, Prasant Mohapat...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 1 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
14 years 1 days ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...