65 search results - page 3 / 13 » A low dynamic power and low leakage power 90-nm CMOS square-... |
TCAD
2008
13 years 7 months ago
2008
Abstract--Design of a suitable power gating (e.g., multithreshold CMOS or super cutoff CMOS) structure is an important and challenging task in sub-90nm VLSI circuits where leakage ...
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
When a signal traverses on-chip voltage domains, a level shifter is required. Inverters can handle a high to low voltage shift with minimal leakage. For a low to high voltage leve...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...