74 search results - page 6 / 15 » A low power approach to system level pipelined interconnect ... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...