444 search results - page 7 / 89 » A low power high performance switched-current multiplier |
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
MICRO
2007
IEEE
13 years 7 months ago
2007
IEEE
VLSID
1993
IEEE
13 years 11 months ago
1993
IEEE
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...