10 search results - page 2 / 2 » A low spur fractional-N frequency synthesizer architecture |
VLSID
2006
IEEE
14 years 8 months ago
2006
IEEE
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...
ICMCS
2006
IEEE
14 years 2 months ago
2006
IEEE
We propose a high performance architecture for fractional motion estimation and Lagrange mode decision in H.264/AVC. Instead of time-consuming fractional-pixel interpolation and s...