21 search results - page 4 / 5 » A low voltage CMOS multiplier for high frequency equalizatio... |
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
VTS
2005
IEEE
14 years 28 days ago
2005
IEEE
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...
ISCAS
2005
IEEE
14 years 28 days ago
2005
IEEE
—A feasibility study is made of an OFDM system based on analog multipliers and integrate-and-dump blocks, targeted at Gb/s copper interconnects. The effective amplitude variation...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order lin...