76 search results - page 7 / 16 » A methodology to improve timing yield in the presence of pro... |
TCAD
2008
13 years 7 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...