76 search results - page 9 / 16 » A methodology to improve timing yield in the presence of pro... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
FTEDA
2006
13 years 7 months ago
2006
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
DAGM
2008
Springer
13 years 9 months ago
2008
Springer
In particle image velocimetry (PIV) a temporally separated image pair of a gas or liquid seeded with small particles is recorded and analysed in order to measure fluid flows therei...