75 search results - page 13 / 15 » A multiple clocking scheme for low power RTL design |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
IPSN
2010
Springer
14 years 2 months ago
2010
Springer
bstract: User-Centric Radio Power Control for Opportunistic Mountain Hiking Networks ∗ Jyh-How Huang1 , Po-Yen Lin1 , Yu-Te Huang2 , Seng-Yong Lau1 , Ling-Jyh Chen2 , Kun-chan La...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
This paper gives an overview of radio interfaces devoted for high data rate Wireless Sensor Networks. Four aerospace applications of WSN are presented to underline the importance ...