In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...