155 search results - page 17 / 31 » A new heuristic algorithm for reversible logic synthesis |
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
AAAI
1993
13 years 8 months ago
1993
Automating the construction of semantic grammars is a di cult and interesting problem for machine learning. This paper shows how the semantic-grammar acquisition problem can be vi...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
TCAD
2008
13 years 7 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...