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» A new heuristic algorithm for reversible logic synthesis
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GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
14 years 25 days ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
TBILLC
2005
Springer
14 years 1 months ago
Natural Logic for Natural Language
We implement the extension of the logical consequence relation to a partial order ≤ on arbitary types built from e (entities) and t (Booleans) that was given in [1], and the deï...
Jan van Eijck
DAC
1996
ACM
13 years 11 months ago
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic
-- We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves s...
Michael Theobald, Steven M. Nowick, Tao Wu
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
14 years 4 months ago
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that ca...
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason ...
DAC
2005
ACM
13 years 9 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill