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DAC
1996
ACM
13 years 12 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
IISWC
2006
IEEE
14 years 1 months ago
Load Instruction Characterization and Acceleration of the BioPerf Programs
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...
Paruj Ratanaworabhan, Martin Burtscher
BIRTHDAY
2005
Springer
14 years 1 months ago
Towards MultiMedia Instruction in Safe and Secure Systems
Abstract. The aim of the MMiSS project is the construction of a multimedia Internet-based adaptive educational system. Its content will initially cover a whole curriculum in the ar...
Bernd Krieg-Brückner
LCTRTS
2001
Springer
14 years 7 days ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
DATE
2008
IEEE
110views Hardware» more  DATE 2008»
14 years 2 months ago
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, J...