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ISCA
1998
IEEE
155views Hardware» more  ISCA 1998»
14 years 1 days ago
A Study of Branch Prediction Strategies
In high-performance computer systems, performance losses due to conditional branch instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issu...
James E. Smith
CASES
2007
ACM
13 years 11 months ago
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
ASAP
2005
IEEE
93views Hardware» more  ASAP 2005»
13 years 9 months ago
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael ...
ISCA
2006
IEEE
158views Hardware» more  ISCA 2006»
14 years 1 months ago
Memory Model = Instruction Reordering + Store Atomicity
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
Arvind, Jan-Willem Maessen