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» A new test pattern generation method for delay fault testing
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ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
14 years 28 days ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
14 years 27 days ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
ICCD
2004
IEEE
134views Hardware» more  ICCD 2004»
14 years 5 months ago
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Pallav Gupta, Rui Zhang, Niraj K. Jha
IOLTS
2005
IEEE
206views Hardware» more  IOLTS 2005»
14 years 2 months ago
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...
Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
ISESE
2002
IEEE
14 years 1 months ago
Elimination of Crucial Faults by a New Selective Testing Method
Recent software systems contain a lot of functions to provide various services. According to this tendency, software testing becomes more difficult than before and cost of testing...
Masayuki Hirayama, Tetsuya Yamamoto, Jiro Okayasu,...