179 search results - page 19 / 36 » A new test pattern generation method for delay fault testing |
COMCOM
1999
13 years 8 months ago
1999
We present a problem of commonly used characterization sequences (CS) for the protocol conformance testing and propose a new test sequence to resolve the problem. The proposed tes...
EVOW
2001
Springer
14 years 1 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
ASPDAC
1998
ACM
14 years 29 days ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
ITC
2002
IEEE
14 years 1 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...