179 search results - page 20 / 36 » A new test pattern generation method for delay fault testing |
INTEGRATION
2006
13 years 8 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
ISSRE
2000
IEEE
14 years 1 months ago
2000
IEEE
Automated generation of test cases is a prerequisite for fast testing. Whereas the research has addressed the creation of individual test points, test trajectoiy generation has at...
DATE
1997
IEEE
14 years 10 days ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...