179 search results - page 23 / 36 » A new test pattern generation method for delay fault testing |
ATS
2003
IEEE
14 years 26 days ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
DATE
2003
IEEE
14 years 26 days ago
2003
IEEE
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
MTDT
2003
IEEE
14 years 25 days ago
2003
IEEE
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
CISS
2011
IEEE
12 years 11 months ago
2011
IEEE
Abstract—Fault detection plays an indispensable role in ensuring the security of smart grid systems. Based on the dynamics of the generators, we show the time evolution of the sm...