179 search results - page 29 / 36 » A new test pattern generation method for delay fault testing |
126
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DAC
2008
ACM
16 years 4 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
128
Voted
DDECS
2009
IEEE
15 years 10 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
132
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ICPR
2002
IEEE
15 years 8 months ago
2002
IEEE
Testing for uniformity of multivariate data is the initial step in exploratory pattern analysis. We propose a new uniformity testing method, which first computes the maximum (sta...
150
Voted
ICCAD
1994
IEEE
15 years 7 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
125
Voted
ATS
2004
IEEE
15 years 7 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...