179 search results - page 5 / 36 » A new test pattern generation method for delay fault testing |
ASPDAC
2004
ACM
14 years 29 days ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
VTS
2008
IEEE
14 years 1 months ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
GLVLSI
2002
IEEE
14 years 15 days ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...