405 search results - page 6 / 81 » A novel cache architecture with enhanced performance and sec... |
HPCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
IJNSEC
2007
13 years 7 months ago
2007
Mobile Ad hoc NETwork (MANET) comprises of nodes, which are free to move randomly, yet cooperate to forward packets between source and destination over a multi-hop wireless networ...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
ANCS
2009
ACM
13 years 5 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...