252 search results - page 6 / 51 » A novel high throughput reconfigurable FPGA architecture |
FPL
2004
Springer
14 years 28 days ago
2004
Springer
A novel configuration bitstream generation tool for a custom FPGA platform is presented. It can support a variety of devices of similar architecture. The tool exhibits technology i...
ARC
2010
Springer
13 years 11 months ago
2010
Springer
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
ISCAS
1995
IEEE
13 years 11 months ago
1995
IEEE
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
RECONFIG
2008
IEEE
14 years 1 months ago
2008
IEEE
– We have implemented in FPGA recently published class of public key algorithms – MQQ, that are based on quasigroup string transformations. Our implementation achieves decrypti...