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» A novel improvement technique for high-level test synthesis
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TC
1998
13 years 7 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
14 years 2 months ago
Incremental Criticality and Yield Gradients
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
DATE
1997
IEEE
92views Hardware» more  DATE 1997»
13 years 12 months ago
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...
A. Dargelas, C. Gauthron, Yves Bertrand
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 1 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
TSE
2010
197views more  TSE 2010»
13 years 2 months ago
A Genetic Algorithm-Based Stress Test Requirements Generator Tool and Its Empirical Evaluation
Genetic algorithms (GAs) have been applied previously to UML-driven, stress test requirements generation with the aim of increasing chances of discovering faults relating to networ...
Vahid Garousi