20 search results - page 3 / 4 » A novel methodology for transistor-level power estimation |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dom...