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» A performance analysis of local synchronization
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IEEEPACT
2009
IEEE
15 years 2 months ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...
159
Voted
WWW
2005
ACM
16 years 5 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
STOC
2009
ACM
159views Algorithms» more  STOC 2009»
16 years 5 months ago
Message passing algorithms and improved LP decoding
Linear programming decoding for low-density parity check codes (and related domains such as compressed sensing) has received increased attention over recent years because of its p...
Sanjeev Arora, Constantinos Daskalakis, David Steu...
147
Voted
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 10 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
146
Voted
DAC
2003
ACM
16 years 5 months ago
Random walks in a supply network
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar