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» A power-configurable bus for embedded systems
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DATE
2003
IEEE
135views Hardware» more  DATE 2003»
14 years 19 days ago
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
Nicola Drago, Franco Fummi, Marco Monguzzi, Giovan...
SAC
2009
ACM
14 years 15 hour ago
The device service bus: a solution for embedded device integration through web services
This paper presents a middleware infrastructure for integration of heterogeneous embedded devices in ubiquitous computing environments. The proposed infrastructure employs the Dev...
Gustavo Medeiros Araújo, Frank Siqueira
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
14 years 4 months ago
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang
SAMOS
2005
Springer
14 years 25 days ago
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hie...
Erno Salminen, Tero Kangas, Jouni Riihimäki, ...
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda