Sciweavers

44 search results - page 4 / 9
» A reuse scenario for the VHDL-based hardware design flow
Sort
View
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 11 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
SAMOS
2010
Springer
13 years 5 months ago
CLI-based compilation flows for the C language
Abstract--Embedded systems contain a wide variety of processors. Economical and technological factors favor systems made of a combination of diverse but programmable processors. So...
Erven Rohou, Andrea C. Ornstein, Marco Cornero
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 19 days ago
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update an...
Massimo Bombana, Francesco Bruschi
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
14 years 8 days ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
ASPDAC
2010
ACM
112views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo