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» A routing algorithm for flip-chip design
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SIGCOMM
2005
ACM
14 years 1 months ago
Fast hash table lookup using extended bloom filter: an aid to network processing
Hash table is used as one of the fundamental modules in several network processing algorithms and applications such as route lookup, packet classification, per-flow state manage...
Haoyu Song, Sarang Dharmapurikar, Jonathan S. Turn...
DAC
2003
ACM
14 years 8 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
14 years 25 days ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
ISPD
1999
ACM
127views Hardware» more  ISPD 1999»
13 years 12 months ago
Buffer insertion for clock delay and skew minimization
 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
X. Zeng, D. Zhou, Wei Li
MOBIHOC
2009
ACM
14 years 8 months ago
Multicasting in delay tolerant networks: a social network perspective
Node mobility and end-to-end disconnections in Delay Tolerant Networks (DTNs) greatly impair the effectiveness of data dissemination. Although social-based approaches can be used ...
Wei Gao, Qinghua Li, Bo Zhao, Guohong Cao